Manufacturer Part Number: CY8C4245AXI-483
- 48MHz ARM Cortex-M0 with 32KB Flash, 4KB SRAM
- 44-pin TQFP with 36 IOs
- 5V with wide-voltage IO options
General Description
PSoC® 4 is a scalable and reconfigurable platform architecture for a family of mixed-signal programmable embedded system controllers with an Arm® Cortex™-M0 CPU. It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing. The PSoC 4200 product family, based on this platform, is a combination of a microcontroller with digital programmable logic, high-performance analog-to-digital conversion, opamps with Comparator mode, and standard communication and timing peripherals. The PSoC 4200 products will be fully upward compatible with members of the PSoC 4 platform for new applications and design needs. The programmable analog and digital sub-systems allow flexibility and in-field tuning of the design.
Features
32-bit MCU Sub-system
- 48-MHz Arm Cortex-M0 CPU with single cycle multiply
- 32 kB of flash with Read Accelerator
- 4 kB of SRAM
Programmable Analog
- Two opamps with reconfigurable high-drive external and high-bandwidth internal drive, Comparator modes, and ADC input buffering capability
- 12-bit, 1-Msps SAR ADC with differential and single-ended modes; Channel Sequencer with signal averaging
- Two current DACs (IDACs) for general-purpose or capacitive sensing applications on any pin
- Two low-power comparators that operate in Deep Sleep mode Programmable Digital
- Four programmable logic blocks called universal digital blocks, (UDBs), each with 8 Macrocells and data path
- Cypress-provided peripheral component library, user-defined state machines, and Verilog input Low Power 1.71-V to 5.5-V Operation
- 20-nA Stop Mode with GPIO pin wakeup
- Hibernate and Deep Sleep modes allow wakeup-time versus power trade-offs
Capacitive Sensing
- Cypress CapSense Sigma-Delta (CSD) provides best-in-class SNR (>5:1) and water tolerance
- Cypress-supplied software component makes capacitive sensing design easy
- Automatic hardware tuning (SmartSense™) Segment LCD Drive
- LCD drive supported on all pins (common or segment)
- Operates in Deep Sleep mode with 4 bits per pin memory
Serial Communication
- Two independent run-time reconfigurable serial communication blocks (SCBs) with reconfigurable I2C, SPI, or UART functionality
Timing and Pulse-Width Modulation
- Four 16-bit timer/counter pulse-width modulator (TCPWM) blocks
- Center-aligned, Edge, and Pseudo-random modes
- Comparator-based triggering of Kill signals for motor drive and other high-reliability digital logic applications
36 Programmable GPIOs
- Any GPIO pin can be CapSense, LCD, analog, or digital
- Drive modes, strengths, and slew rates are programmable Five different packages
- 44-pin TQFP
Extended Industrial Temperature Operation
- –40 °C to + 105 °C operation
PSoC Creator Design Environment
- Integrated Development Environment (IDE) provides schematic design entry and build (with analog and digital automatic routing)
- Applications Programming Interface (API) component for all fixed-function and programmable peripherals
Industry-Standard Tool Compatibility
- After schematic entry, development can be done with Arm-based industry-standard development tools
